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    1,356 verilog projects trabajados encontrados, precios en USD

    necesito transmitir datos numericos entre la fpga ne...ingresado en formato decimal en el lcd 7 segmentos, adicional a eso que esta información sea transmitida via puerto uart al computador. los entregarles son el codigo hecho en verilog,( make file, archivos.v ) ademas de brindar una breve explicacion del trabajo realizado. hay un plazo de 15 dias.

    $32 / hr (Avg Bid)
    $32 / hr Oferta Promedio
    6 ofertas

    Necesito para nuestro equipo de 15 ingenieros incorporar dos nuevos ingenieros con ilusión, cierta experiencia y conocimientos en VHDL/Verilog y microprocesadores. Es trabajo a tiempo completo y con estabilidad (2 años). Ubicación: Sevilla y Albacete. Uno en cada sitio.

    $23409 - $58522
    $23409 - $58522
    0 ofertas
    FPGA TCPIP implementation 5 días left
    VERIFICADO

    FPGA TCPIP implementation using Verilog

    $21 / hr (Avg Bid)
    $21 / hr Oferta Promedio
    12 ofertas

    Verilog digital logic deisgn simple work

    $23 (Avg Bid)
    $23 Oferta Promedio
    18 ofertas

    I have Altera Verilog source code. This is crosspoing from Altera. Add a special feature (essential) to enable any one input (DI) to connect simultaneously to ALLoutputs (DO). Likely part would be EPM570T100I5. You can get source code follow link. [iniciar sesión para ver URL]

    $46 (Avg Bid)
    $46 Oferta Promedio
    16 ofertas

    I have a simple Verilog project. This is very simple. I attached a Logic diagram. Please reference this. Thanks for advance.

    $23 (Avg Bid)
    $23 Oferta Promedio
    22 ofertas

    I want to Verilog programmer. This job i This is very simple. I attached image for logic. You can write code on QuartusII. and then the code must be compiled. Please check image and place bid. Thanks.

    $22 (Avg Bid)
    $22 Oferta Promedio
    17 ofertas
    Verilog design project Finalizado left

    Verilog and Quartus based programming. The project requires a working alarm clock with certain specifications to be met when certain switches are activated.

    $21 / hr (Avg Bid)
    $21 / hr Oferta Promedio
    20 ofertas

    Program counter to be simulated with testbench and implemented on De0-cv fpga. Please see file for exact specificiations and criteria.

    $131 (Avg Bid)
    $131 Oferta Promedio
    19 ofertas

    Design an Alarm Clock using Verilog and implement it on DE0-CV board using HEX display. Design Specifications for the Alarm Clock • Time should be displayed on the 6-digits of the 7-segment display (HHMMSS). o The left two digits will be the hour, middle two digits will display the minutes and the right two digits will display the seconds. (the period

    $122 (Avg Bid)
    $122 Oferta Promedio
    13 ofertas
    System Verilog Trainer Finalizado left

    We are looking for a System Verilog Training for few Engineers in our premises.

    $1983 (Avg Bid)
    $1983 Oferta Promedio
    5 ofertas

    Design Pipeline processor for RISC based instruction set on Xilinx ISE verilog for Spartan 3E board. Instruction set is given and we need certain kind of output based on designed assembly code. Code should be loaded on Instruction memory and it's already done. we have only 2 days for that but processor is 8bit and instruction is 16bit

    $100 (Avg Bid)
    $100 Oferta Promedio
    8 ofertas

    ALU The ALU should be coded using these integer operations *, +, -, and /. Register File The register file must be implemented in a separate module. Hex display The hex display must be implemented using a function that converts digits to 7 segment display segments.

    $123 (Avg Bid)
    $123 Oferta Promedio
    20 ofertas
    Alarm clock Verilog Finalizado left

    Design an Alarm Clock using Verilog and implement it on DE0-CV board using HEX display.

    $184 (Avg Bid)
    $184 Oferta Promedio
    15 ofertas

    i need to design 8 bit pipeline line processor in xilinx ISE. It should be in verilog. there is 3 type of instruction set.

    $86 (Avg Bid)
    $86 Oferta Promedio
    5 ofertas

    Hello, I need some help with Verilog coding. I already have the code but Im having errors and cant compile it. Also, I need hepl with implementing testbench. Teamviewer required to debug the code and I can send you the document to take a look at the project.

    $106 (Avg Bid)
    $106 Oferta Promedio
    11 ofertas

    Hi, I have opencv python programs want to implement them on the ZYNQ SoC. To be in precise want to implement custom object detection(using opencv, tensorflow) on to ZYN...them on the ZYNQ SoC. To be in precise want to implement custom object detection(using opencv, tensorflow) on to ZYNQ board. And also converting the python program to VHDL/Verilog.

    $132 (Avg Bid)
    $132 Oferta Promedio
    7 ofertas

    - Development Environment Tool : Xilinx Vivado and SDK Latest version Device : Xilinx Zynq7045 HDL : Verilog HDL Required IP Module :HDMI_RX, HDMI_TX Using PG235 [iniciar sesión para ver URL] Using PG236 [iniciar sesión para ver URL]

    $128 (Avg Bid)
    $128 Oferta Promedio
    3 ofertas

    Hello, I have the complete knowledge of languages like shell, perl, python, verilog and system verilog.

    $72 (Avg Bid)
    $72 Oferta Promedio
    1 ofertas

    Hi Iqra Software .., I noticed your profile and would like to offer you my project. We can discuss any details over chat. How many of your team members ar...Iqra Software .., I noticed your profile and would like to offer you my project. We can discuss any details over chat. How many of your team members are experienced with Verilog FPGA programing?

    $42 / hr (Avg Bid)
    $42 / hr Oferta Promedio
    1 ofertas