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Design a simple CPU using Verilog

$30-250 SGD

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Publicado hace más de 10 años

$30-250 SGD

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This is a school assignment that requires us to design a simple 5-stage pipeline CPU. It should be able to detect data hazard and insert bubbles into the pipeline accordingly. This is the description of the assignment: [login to view URL]
ID del proyecto: 5115568

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11 propuestas
Proyecto remoto
Activo hace 10 años

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11 freelancers están ofertando un promedio de $285 SGD por este trabajo
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Dear sir, I have more than 5 years experience in digital design using verilog I have already worked in similar project before please read the reviews written on me for similar CPU design project
$244 SGD en 7 días
4,9 (471 comentarios)
8,0
8,0
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Dear Hiring Manager, I have already built similar processor (CPU) during my BS engineering. I can help you do this. You can have a look at my profile to see how beautifully I have done all my projects, and read reviews my clients have posted. I provide free 15-days support to my clients so that they verify the design and enjoy the real work (if they are students I provide this support so that they can prepare their viva etc. and get excellent grades). So, I guarantee you will be 110% satisfied with my work and become permanently my client. The price is negotiable so feel free to contact me. Regards Faraz Ahmad
$1.000 SGD en 50 días
4,9 (28 comentarios)
5,4
5,4
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Hi I am an electronic undergraduate. I am very good at verilog. I recently developed 8051 microcontroller using verilog. I can help you.
$277 SGD en 8 días
5,0 (6 comentarios)
4,3
4,3
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Hi, Verilog HDL expert here with 15+ years experience (since early 1998). 36 yo, really old in this field and experienced ^_^ Have designed more than 20 CPUs and overall 125+ custom designs including FFT, DCT, motion estimation, motion compensation, MSF receiver, DCF77 receiver, bus encoders, multiple ASIPs/CPUs incl. the research ByoRISC processor. Guaranteed quality of work and delivery within one work week (7 calendar days).
$244 SGD en 7 días
5,0 (2 comentarios)
4,0
4,0
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Hi, I am a graduate in EEE.I have 15 years of experience in programming,electronic design and teaching.I can do this work for you. Thanks and Regards, Prasad.M
$155 SGD en 10 días
5,0 (7 comentarios)
3,8
3,8
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I can do your project.i have two year plus experience of this field....................................................
$230 SGD en 3 días
5,0 (5 comentarios)
2,9
2,9
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Hi , I can deliver the project to you on well in time. Have already done this and have got the files almost ready. Just need to check them again for you. I have quite well experience in computer architecture with industrial experience in leading processor vendors Hope to hear from you soon.
$135 SGD en 3 días
5,0 (2 comentarios)
0,7
0,7
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Hello. I've designed several simple CPU's. The description says there are two phases - PhaseOne and PhaseTwo(with shared memory for instructions and data). What phase do you need? I think your final grade primarily depends on final report and your ability to answer detailed questions. So it's going to be a lot of conversation with us. Also I'm ready to prepare the testing methodology as the description asks. According to the description there should be Verilog modules for the instruction and data memories provided to you.
$300 SGD en 5 días
0,0 (0 comentarios)
0,0
0,0
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I made a CPU last year for my assignment, I can do it for you again. Verilog is my favorite hardware design language.
$155 SGD en 3 días
0,0 (0 comentarios)
0,0
0,0

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Bandera de SINGAPORE
Johor Bahru, Singapore
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Miembro desde abr 3, 2013

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