Designing a Debug logic in Verilog
₹1500-12500 INR
Pagado a la entrega
Hi,
I have a processor designed and now i need to design a debug logic for that processor in Verilog. You need to design registers for halt and run and when you get a halt signal from outside you need to halt the processor and when you get a Run signal from outside it should continue running.
If you are interested i can provide you more details.
Regards,
Dinesh
Nº del proyecto: #14136867
Sobre el proyecto
Adjudicado a:
Hello! Thank you for inviting me to this project. Yes, the project sounds really interesting. I would love to work on it. Please do contact to discuss further. Thank you!
14 freelancers están ofertando un promedio de ₹7672 por este trabajo
Dear customer, I am really happy to help you out of this project. I would like to introduce that I am an freelancer with 100% JOB COMPLETED in VHDL/VERILOG. I am really suitable for job description: First: I a Más
skfjlaskjglkajglkajroiweurl;kjglkjgklajsklgjaslkdgjlkasjgoiweurjlskjflksjflksjflksfmklagmdgmalkfslkfk
Hello, Thanks for your invitation to bid on this project. I can execute this project, but I am currently occupied with my existing commitments. I can take up this project only in August. Please let me know if th Más
i have designed a microprocessor in verilog and i can help u in this regard please share thew complete details and design spec.
I am familar with computer architecture. The problem is how is your CPU processor designed. What ISA are you using ? Debug logic is mostly on PC, CSR registers. Please let me know about your processor architec Más