Designing a Debug logic in Verilog

Completado Publicado hace 6 años Pagado a la entrega
Completado Pagado a la entrega

Hi,

I have a processor designed and now i need to design a debug logic for that processor in Verilog. You need to design registers for halt and run and when you get a halt signal from outside you need to halt the processor and when you get a Run signal from outside it should continue running.

If you are interested i can provide you more details.

Regards,

Dinesh

Verilog / VHDL

Nº del proyecto: #14136867

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14 propuestas Proyecto remoto Activo hace 6 años

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raulbehl

Hello! Thank you for inviting me to this project. Yes, the project sounds really interesting. I would love to work on it. Please do contact to discuss further. Thank you!

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14 freelancers están ofertando un promedio de ₹7672 por este trabajo

ducdctoandh

Dear customer, I am really happy to help you out of this project. I would like to introduce that I am an freelancer with 100% JOB COMPLETED in VHDL/VERILOG. I am really suitable for job description: First: I a Más

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kulwantsingh16

A proposal has not yet been provided

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prakashddit

Have 2.5+ years of Verilog and System Verilog experience! Bid can be negotiable.

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sajjadahmed19

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nikj1101

hi. experienced in verilog/vhdl. get back to me if interested

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nirajmahapatro

Hello, Thanks for your invitation to bid on this project. I can execute this project, but I am currently occupied with my existing commitments. I can take up this project only in August. Please let me know if th Más

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techoviz

Hello, We are a team of embedded hardware and software professionals with experience in verilog/vhdl programming and testing. Would like to know more about the project. Looking forward to work on this project. Más

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guruuvce12

i have designed a microprocessor in verilog and i can help u in this regard please share thew complete details and design spec.

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HarryToyota

I am familar with computer architecture. The problem is how is your CPU processor designed. What ISA are you using ? Debug logic is mostly on PC, CSR registers. Please let me know about your processor architec Más

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Peacock12

I have designed many modules in verilog. I can definitely help you with this project. Please contact me through freelancer if you want to discuss more. Relevant Skills and Experience I have done RTL coding, synthesis Más

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