A Simple State Machine including Test bench and memory block
$30-250 AUD
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Publicado hace casi 12 años
$30-250 AUD
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Implement a simple state machine that controls the sequencing of the line LdA, LdB and LdS. The objective is to enable each of these at
successive clock cycles such that you are able to load register A in cycle 1, then B in cycle 2 and to examine the result in cycle 3. See the
timing diagram below
The DE1 board includes an SRAM chip, called IS61LV25616AL-10, a static RAM with a
capacity of 256K 16-bit words