System Verilog- NOC design (8 bit split bus)

Cerrado

12 los freelancers están ofertando un promedio de $26 para este trabajo.

ahmedmohamed85

A proposal has not yet been provided

$30 USD en 1 día
(239 comentarios)
7.4
$25 USD en 1 día
(77 comentarios)
6.1
raulbehl

Hello! Please check my reviews to know a bit about me! Thank you

$24 USD en 2 días
(20 comentarios)
4.8
$30 USD en 2 días
(10 comentarios)
3.8
rohi1710rohi1710

Hi, -FPGA design engineer since last 7 years -Expertise in verilog/VHDL Please find below details of the projects TSMAC Hardware acceleration(3months) The project is to develop hardware acceleration block for TS Más

$25 USD en 1 día
(4 comentarios)
3.8
$30 USD en 1 día
(12 comentarios)
3.7
smk55

I am Hardware Design Engineer have done MSC system on Chip, University Southampton, UK. I have more than 10 years experience in digital design and well acquainted with ISE 14.5, NCverilog, Vivado 2013.4, Altera Quartus Más

$25 USD en 1 día
(4 comentarios)
3.4
$30 USD en 1 día
(4 comentarios)
3.4
abuzduga

What exactly do you require ? A verification environment ? Will you provide the design ? Or do you also want the design ?

$15 USD en 10 días
(1 comentario)
2.3
nitulsodlan1702

Hello, I can do this project. I am expert in FPGA, VHDL, Verilog. I have done no of project on this technology. Please open your chat box for more discussion. I have 4 year experience in this field. I can do your pro Más

$25 USD en 1 día
(0 comentarios)
0.0
dangluonghoangvu

I have module IP for CRC calculation. i think it easy with me...please contact me to get draft version about CRC. Thanks Vu

$25 USD en 1 día
(0 comentarios)
0.0
burhanmudassar

Over 2.5 years of experience in Verilog RTL Design, Microcontroller Projects and Algorithm Design in MATLAB in Industry and Academia. My past projects include: - PHY Layer Design on FPGA for Software Defined Radio P Más

$25 USD en 1 día
(0 comentarios)
0.0