VHDL Division with Sequential Control

Design a Division Unit (DIV) to be attached to a bus structure that will provide data and accept results and other values. The data provided will be the divisor and the dividend. The results will be quotient and reminder.

The DIV will operate on two integers, call them A and B. Thus, there are control lines writing to and reading from registers A and B. That is, the bus structure and protocol will be used to both fill and read registers A and B. When a division is requested, then another bus transaction will initiate the division, and your unit must take two integers and calculate the equivalent of A/B. The quotient must be in a register known as the MQ register, and the reminder in a register known as the ACC register. The coding scheme for integers is unsigned binary, and hence the algorithms that you use will not need to be capable of taking care of signed numbers.

This project consists of designing the divider. The design must be done with modules described in VHDL and combined appropriately. A simple division algorithm that implements the device will be provided (State Diagram).

## Deliverables

1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done.

2) Deliverables must be in ready-to-run condition, as follows (depending on the nature of the deliverables):

a) For web sites or other server-side deliverables intended to only ever exist in one place in the Buyer's environment--Deliverables must be installed by the Seller in ready-to-run condition in the Buyer's environment.

b) For all others including desktop software or software the buyer intends to distribute: A software installation package that will install the software in ready-to-run condition on the platform(s) specified in this bid request.

3) All deliverables will be considered "work made for hire" under U.S. Copyright law. Buyer will receive exclusive and complete copyrights to all work purchased. (No GPL, GNU, 3rd party components, etc. unless all copyright ramifications are explained AND AGREED TO by the buyer on the site per the coder's Seller Legal Agreement).

## Platform

VHDL

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Nº del proyecto: #3414842

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