AHCI testbench in SystemVerilog

Dear sir, I have more than 7 years experience in digital design and verificatioon using VHDL/verilog and systemverilog, i am very interested in working on your project, waiting your reply, best regards;

Hello! If you have digital design projects I can help you right away! I have 8 years experience in designing digital logic circuits using VHDL and implementing them in FPGAs. I was a digital design engineer at Grenoble Institute of Technology! Right now I am a teaching assistant at an important university in Europe. I teach the digital logic design and VHDL modules laboratories! Have a nice day!

Hello! I can be at your assistance for 20h/week in the following 2 month. The bid is for 170 work hours at 8.5$/hour wage. I would send you may resume, so I can prove that I'm fot for your requirements. Regards, Botond

Hi, I am a fresh HDL designer to use verlog,systemverilog,vhdl to live in Seoul. I am studying systemverilog verification code,now. Could you give me a chance to verify your design code? Though, I have small qualification , I want to try to code systemverilog testbench verifcation. If your code is very difficult, you should know I can not do it . Thanks,

Hi Myself Shobhit Kapoor , I have 10+ Years of experience in FPGA/ASIC Design and Verification , will provide you best reats with quality work , I am little new to freelancer.com but have very good reputation in oDesk and Guru. I have good Expertise in Host Controller Interfaces i.e. AHCI , SATA ,ATA ,eSATA , as well I have more than 5+ Yrs of Experience in SystemVerilog and OVM/UVM ? are you expecting UVM Environment or SystemVerilog based testbench is fine for you ? Please let me know how can we take this further ? I may need some more specification related questions . Thanks Shobhit Kapoor

Hi, I have a Front-End verification and design experience of 4+years and currently iam working in a top EDA company. Iam first time biding and really looking forward to complete the project, i have a 2 weeks of free time. I have worked in System verilog for 5 industrial projects and use it very frequently in my work, iam good at writing assertions and have also worked with Specman. I have signed-off verification on my project(D-PHY using Specman) this week and have 2 weeks of free time. I can provide you the best code and verification environment in system verilog with good documentation starting from verification Plan to environment documentation. Also plan on coding functional coverage in SV. Hope you find my profile suitable for your requirement. Thanking You Regards Madhu Kiran.