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$250-750 USD

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Generate System Verilog UVM testbench and HTML tables from XLS describing register description of a IP Skills needed - Hardware design, SystemVerilog, UVM, Python, HTML

Electronics

Python

Verilog / VHDL

ID del proyecto: 6097864

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Activo hace 10 años

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3 freelancers están ofertando un promedio de $574 USD por este trabajo

@hemangvp

i have work exp on SystemVerilog and OVM based TB development. Also know Perl and C++ . Have experience on Hardware Logic design knowledge too.

$444 USD en 10 días

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@shobhitkapoor

Hi I have seen your requirement and sounds very interesting to me and basically belongs to my skill set i.e. which is UVM and SystemVerilog , I have 10+ years of Design and Verification Experience and worked for top notch Chip and EDA Companies , Basically I understand of generating concept of UVM Testbench but are you expecting the Test-bench should be generic which can written for any IP ? or you want to right for specific IP only ? I would prefer to write product in perl , even I wrote personal template generator & code generator for my personal usage. it is possible to write basic read/write based auto generated test bench , it would be great if you send me your idea in blocks what exactly you want to generate from register description ? please provide some more details about work Thanks Shobhit K.

$722 USD en 60 días