Build a 16-bit MIPS-L single cycle processor

We need to Implement the MIPS-L single-cycle design using Verilog that can run the R-type (add, sub, and, or and slt), lw, sw, beq, addi, j, jr and jal instructions. Notice that the MIPS-L has a reset input. If reset = 0 then the MIPS-L will run as normal. If reset = 1, then the MIPS-L has its PC value set to 0. Your test bench should instantiate the MIPS-L module and the memory. It will also generate the clock signal and the reset. It will display the outputs “pc-out”, “alu-result”, and display the contents at certain memory locations.