implement one project with system verilog in Zynq

€8-80 EUR

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hace más de 6 años

€8-80 EUR

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I need to implement the threshold block and verify that with two AXI VIP as you can see in the picture. I need a testbench which generates random numbers between 500 to 1000 and the threshold block count the number of data more than 500. the project can be done also with ILA but at this point I prefer system Verilog. Xilinx has a tesbecnh example which helps to write a code quickly.

Electrical Engineering

FPGA

Verilog / VHDL

ID del proyecto: 15598742

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3 propuestas

Proyecto remoto

Activo hace 6 años

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3 freelancers están ofertando un promedio de €83 EUR por este trabajo

@atharbaig6167

Hi there, verilog and FPGA exert here. I can do this project within your required time and budget. Please contact. Thanks Relevant Skills and Experience FPGA, verilog Proposed Milestones €90 EUR - Complete work

€90 EUR en 4 días

4,6

(22 comentarios)

4,3

@vraigur

1. To generate pseudo random numbers, Iam planning to use a LFSR. I have other ways in mind though. I assume that the pass through block for axi verification IP is inside the core Threshold_0. Relevant Skills and Experience System Verilog, Xilinx Vivado, Low power vlsi Architectures, FPGA Flow. I have a work experience of 2 years. Proposed Milestones €48 EUR - architecture design in a day, verilog implementation in 3 days, Verification 3 days synthesis 1 day.

€48 EUR en 10 días