Spi slave connect with wishbone master by VHDL for FPGA

I am trying to build a core (IP) that includes communication between SPI slave and wishbone master. I have written the state machine for both of them. also, I have the codes for both. The issue is that I don"t know how to make both of them communicate in a correct way. I have tried a lot but I was not able to do it. I wish that I can find someone that able to make it work so I can learn from it. I can help you with anything you need also I can provide the codes for you. Please, be aware that I am not willing to pay a lot for this so please make your price reasonable and cheap.