design a pipeline for a proposed instruction set architecture.

This project involves the design a pipeline for a proposed instruction set architecture. The design will include such elements as: the number of stages; what resources are available to each stage; what forwarding is allowed for each stage; whether the pipeline is in-order or out-of-order issue. The project requires an analysis of the performance and cost of the pipeline for a set of small sample programs. The designer will select a design goal target and then meet that goal under constraints given by the instructor. 1The ISA The ISA will be based on a RISC model. It is a fixed sized instruction set, with a load/store model. The instruction set includes floating point instructions. For purposes of the project, the instruction encoding mostly irrelevant. 1.1Integer Instructions The ISA supports all of the standard ALU functions: basic arithmetic [addition, subtraction, multiplication, and division], logical instructions [and, or, not, xor], bitwise [and/or/xor/not] instructions, shifts, and rotations. All of these instructions are single cycle with the exception of multiply and divide, which require two and four cycles, respectively. The arithmetic, logic, and bitwise instructions are three register operand, with one register the destination and the other two the sources. The not instructions, however, only requires two registers. The shift and rotation instructions require two register operands: the register to be shifted or rotated and a register containing the number of bits to shift or rotate.