I would like to bid this job because I am really suitable for job description:
First: I am an C++/C/Mathlab/Electronics engineer who is very familiar with C++/C/Mathlab/VHDL/Verilog. In fact, I have done so many project of VHDL/Verilog(Karatsuba multiplier, Nintendo design, encryption algorithm like Sax Hash, Bernstein Hash, HummingBird...Especialy, I participated in a Walker Recognition project(data from Camera to Human Detection(image processing-HOG feature and Adaboost) and display in VGA). Besides,,I implemented the image conpression (wavelet transform).
Especially, I have done some project related to VLSI, These needs to add some constrains in the gate delay, after that we can see the change in simulation, compared to the version which doesn't have gate delay.
Finally, I am very good in English (IELTS 6.0) and I have several year of researching so I can fully understand your requirement and understand fully about the papers.. Please contact me and let me know if you want any special requirement.
Thank you.