am looking for someone good with verilog or system verilog who can implement the following design

I am looking for someone who is good with verilog and system veriliog who can do the following : The idea of this application is to equifill rectangles in individual rows based on comparing strip heights and program heights. The design should use a decoder. for example : if you have row of height strip 8, it is checking 9, and 10 so it will compare 8 and 9 and then it will compare the minimum of 8 and 9 with 10. A table on page 2 of the attached document explains these comparisons with further examples. But, each time the program should only perform 3 comparisons. The program needs to use 8 clock cycles strictly. It needs to be a design that can be optimized. It needs to fit in the top level module (M216A_TopModule (2).v) that I have attached and it needs to work for all cases in the testbench that i have attached as well (see M216_tb.v) here. The file [login to view URL] gives the desin specification. you can use two FSMs and pipeline them together in your design. Do not do the comparison and the adder work together in one clock cycle, do them in separate clock cycles. So you have one clock cycle for reset, two for carrying out the comparisons of the three strips that you will compare at once as per page two, one for adding the strip width and subtractign the strip width from the program width to see if there is space and if there is no space, one clock cycle to increase a strike counter. [login to view URL] shows the results of each test case that have to be passed. [login to view URL] shows the strip IDs that are entered for each test case in the testbench.