SERDES RTL DESIGN

Cerrado Publicado hace 5 años Pagado a la entrega
Cerrado

I'm looking for an experienced SERDES engineer to design a SERDES PCS on ASIC. This PCS will be connected to a PHY(PMA) IP, encoding the data with 8b10 protocol and then transmitting (no receiving) the data out through the PMA, 5Gbps. The data will be received by a Xilinx FPGA GTH Transceiver and then decoded. Therefore the PCS logics shall be compatible with the GTH Transceiver.

Your tasks are

1. Write the PCS RTL code

2. Provide a compatible GTH transceiver configuration/RTL.

3. Provide guidance on verification of the whole link channel.

Ingeniería eléctrica Electrónica FPGA Verilog / VHDL

Nº del proyecto: #18004382

Sobre el proyecto

9 propuestas Proyecto remoto Activo hace 5 años

9 freelancers están ofertando un promedio de $56 / hora por este trabajo

ducdctoandh

Dear customer, I am really happy to help you out of this project. I would like to introduce that I am an freelancer with 100% JOB COMPLETED in VHDL/VERILOG. I am really suitable for job description: First: I a Más

$55 USD / hora
(89 comentarios)
6.4
FernandoAGV

I am Senior Electronic Engineer with advanced knowledge of digital signal processing, and experience in the design of embedded systems in real time implemented with DSP, FPGA and Microcontrollers. In my experience i Más

$50 USD / hora
(5 comentarios)
6.1
IntegraSources

Hello, I see that you’re looking for an experienced SerDes engineer to include SerDes block into ASIC, and would like to offer our team to get this done efficiently and in reasonable time. We are a team of elect Más

$55 USD / hora
(20 comentarios)
5.2
eopskzs

I am an experienced digital design engineer. I have designed LVDS and HDMI links before for video transmission onn spartan6-virtex5-kintex and zynq devices. Drop a line over chat if you have any questions. best rega Más

$75 USD / hora
(6 comentarios)
4.2
prakashddit

I have successfully done communication using GTX, and I have exposure to GTH also. I have knowledge of PMA + PCS. I can do your project.

$55 USD / hora
(7 comentarios)
3.7
NienYi07

Hi, i am an experience hardware designer in Silicon Valley. Have designed hardware for high speed Serdes using 8b/10b encoding and PCS layer PHY used in data center applications. Familiar with both VHDL and Verilog, di Más

$55 USD / hora
(0 comentarios)
2.7
Holguer

The job position posted on the company’s webpage is a good fit for me, given my experience in the field of FPGAs, and Embedded Systems. I am confident that I fulfill all the requirements that the company is looking for Más

$55 USD / hora
(0 comentarios)
0.0
tienthanhkt09

1.0 year of experience in Analog layout design 3.0 years of experience in FPGA and Embedded System Familiar with device driver development with many interfaces (I2C, UART, SPI, AXI protocol), extensive knowledge abo Más

$50 USD / hora
(0 comentarios)
0.0