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    706 altera de2 nios qsys trabajados encontrados, precios en USD
    Traffic Control System Finalizado left

    Traffic Control System (Two intersection road) using VHDL in Quartus II. Write Code, test bench and simulate in Modelsim Altera. Draw Flow diagram or ASM chart and Mnemonic document state diagram.

    Electrónica Ingeniería FPGA Microcontrolador Verilog / VHDL
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    VHDL project 'Analog to digital converter' By using a sensor for FPGA kit. Finalizado left

    In this project I want to see how the ADC works in FPGA kit .. with any sensor LED or temp. The board is ALTERA Cyclone IV EP4CE6e22cb

    Ingeniería eléctrica Electrónica FPGA Microcontrolador Verilog / VHDL
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    aplicativo energia solar Finalizado left

    preciso criar um aplicativo para conectar nos aparelhos solar para puxar o consumo do cliente ver detalhes quanto tempo gero energia , gráfico de produção de energia tem que ser dois app um para cliente visualizar quanto esta a produção e outro app para criar o acesso do cliente altera a senha do cliente e visualizar todos o cliente quanto estão consumido

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    Plugin Woocomerce de Tabela de Preço -- 2 Finalizado left

    ...estão no Woocommerce. Seria mais ou menos uma lista criada por blocos e linha, blocos seria para especificar manualmente uma categoria e na linha o nome do produto colocado manualmente e uma opção para procurar e selecionar o produto que ser vinculado a essa linha, uma vez vinculado vai aparecer na frente o preço e sua variável para ser selecionada caso tenha e uma vez alterado o preço ele também altera e salva no Woocommerce, nessa opção era bom ter um botão para salvar e excluir a linha. Uma vez a linha feita logo abaixo poderia ter o botão de mais para adicionar novas linhas ou blocos. Tudo isso feito é preciso gerar um shortcode ou algo do tipo para gerar um html e ser publicado em uma pagina...

    CSS HTML MySQL PHP WordPress
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    Need a computer science tutor for practicals Finalizado left

    Need help in completing this NIOS Practicals

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    HPS DE10 Nano support Finalizado left

    Hello, I’ve just received my DE10-Nano board and I’ve already created a project in VHDL, Qsys and application level code in *.c (simple LED). I already know how to create the *.rbf, the preloaded file, the and all the file necessary to boot out of the uSD card. I already have an installation for the Quartus (18.1), SOC EDS and Putty. What I don’t know is how to write every thing into the uSD card partitions and to run a complete simple LED code. Can anybody help me to complete a that ~5% that I have left for fully SOC code? *A preference is to those who have a the DE10 board. Idan

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    Quartus Altera/INTEL Finalizado left

    Looking for a tutor on Quartus Altera/Intel MAX10 FPGA device. Knowledge of QSYS, Platform designer, Eclipse, HDL/VHDL. Embedded system control design using FPGA. Closed loop control ADC sampling, PI controller , PWM generation in HDL/VHDL.

    Altera Quartus Digital Signal Processing FPGA Microcontrolador Verilog / VHDL
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    Content writing for website Power electronics converter battery charging. Finalizado left

    Looking for website content for Power electronics converter for battery chargers for EV market. Magnetics design , Embedded software FPGA. Altera/Intel VHDL.

    Content Marketing Redacción de contenidos Electrónica Power Converters Diseño de sitios web
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    VHDL SD card implementation Finalizado left

    Hello, In my project I need to store data on my FPGA Altera EVMs. The data must be stored on a non-volatile device (power done can occur at all time). To do that, I need to implement an interface to the on board uSD card. Here are some specification: 1. SD Card: Class 10, 2GB. 2. Min write speed: 200Byte every 1ms (effective) ~1.6Mbps. 3. Read speed: 10Mbps (Flash all mode) 4. All VHDL (NiosII- only when guaranteed performance). 5. Full Duplex- Optional. 6. Target: DE10-Nano and DE2-115. 7. Delete all data function: optional. Thanks, Idan

    FPGA Verilog / VHDL
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    Project for Worldfast Translator24 Finalizado left

    Hyundai smallest SUV Casper (AX1) coming in global & Indian market _ Hyundai Casper will be smaller than Hyundai Venue _ Casper could be based on K1 platform from new santro & Grand i10 Nios _ Casper is expected to get 2 engine options; a 1.2 litre petrol from Grand i10 Nios & for lower variants a 1.1 litre petrol engine _ It could get Venue's 1.0 turbo petrol in some markets _ Hyundai Casper global unveil is expected in September 2021 & It will be first launched in Korea, then in India _ ? What are your thoughts on Hyundai smallest SUV Casper? _ ? Will you choose this over Maruti Suzuki Ignis, Mahindra KUV100 & Upcoming Tata HBX ?

    English (UK) Translator English (US) Translator Traductor de Coreano Traductor de español Traducción
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    resolver problemas de execução de sketchup Finalizado left

    Preciso de ajuda para poder trabalhar com meu programa, tenho placa de video geforce940mx configurações compativeis, e o programa trava muito, baixei um programa para fazer checkup dos requisitos e la diz que estou usando uma placa intel e que poderia melhorar usando a nvidea, mas faço a alteração nas definições da nvidia, e faco o checkup novamente mas nao altera.

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    Digital electronic -- 2 Finalizado left

    You are required to design and implement a state machine based control system for a car barrier system. It will be required to take simulated inputs from sensors that detects the presence of a car and requires a coded entry system. It must suitably control the barrier and lights to allow safe progress of the car. This must be implemented as a fully functioning desig...design and implement a state machine based control system for a car barrier system. It will be required to take simulated inputs from sensors that detects the presence of a car and requires a coded entry system. It must suitably control the barrier and lights to allow safe progress of the car. This must be implemented as a fully functioning design verified by simulation and can be demonstrated on the DE2-115 developmen...

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    Electronic Finalizado left

    ...design and implement a state machine based control system for a car barrier system. It will be required to take simulated inputs from sensors that detects the presence of a car and requires a coded entry system It must suitably control the barrier and lights to allow safe progress of the car. This must be implemented as a fully functioning design verified by simulation and can be demonstrated on the DE2-115 development boards A detailed brief is given at the end of this document. The deliverables required from this assessment are: This design report must detail the functionality and operation of your state machine. It should contain a state diagram and an explanation of how this meets the functional requirements of the specified problem. It should also provide details ...

    Diseño de circuitos Ingeniería eléctrica Electrónica Ingeniería Verilog / VHDL
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    Digital electronic Finalizado left

    You are required to design and implement a state machine based control system for a car barrier system. It will be required to take simulated inputs from sensors that detects the presence of a car and requires a coded entry system. It must suitably control the barrier and lights to allow safe progress of the car. This must be implemented as a fully functioning desig...design and implement a state machine based control system for a car barrier system. It will be required to take simulated inputs from sensors that detects the presence of a car and requires a coded entry system. It must suitably control the barrier and lights to allow safe progress of the car. This must be implemented as a fully functioning design verified by simulation and can be demonstrated on the DE2-115 developmen...

    Diseño de circuitos Ingeniería eléctrica Electrónica Ingeniería Diseño PCB
    $203 (Avg Bid)
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    FPGA I2C module Finalizado left

    prepare a I2C module for Altera FPGA

    Ingeniería eléctrica Verilog / VHDL
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    Alterar parâmetros de aplicação já desenvolvida de automação de whatsapp Finalizado left

    - A aplicação parou de funcionar devido a alteração de nomes de parâmetros do WhatsApp. - Necessário verificar quais parâmetros pararam de funcionar e altera-los de acordo com os atuais - Criar documentação técnica e funcional da aplicação já desenvolvida para melhorar o suporte. - Funcionalidade da aplicação: A aplicação já desenvolvida apenas exporta os números das conversas do whatsapp que não possuem na agenda (novos números)

    AI/RPA development Process Automation Python
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    VHDL simple set of PROJECTs to simulate Finalizado left

    VHDL , QUARTUS , MODELSIM ALTERA, QUESTASIM, UP DOWN COUNTER , COUNT ZERO COUNTER, CLOCK GENERATOR, RGB CONTROLLER. STATE MACHINE ...

    Diseño de circuitos FPGA FPGA Coding Verilog / VHDL
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    Quartus 2019.1 Project development Finalizado left

    Hello All, I need to develop a project with Quartus 2019.1 software tool. I need to create a schematic based design approach for DE2-115 evaluation module. Hardly 2Hour job. Please bid if you're completely aware of the design flow with Quartus 2019.1 software. Having DE2-115 evaluation module will be added advantage.

    FPGA FPGA Coding Verilog / VHDL
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    INTERFACE a ADC with TERASIC DE4 board Finalizado left

    The AD 9254 is to be interfaced with TERASIC DE4(Altera startix IV) in DSP builder platform

    Ingeniería eléctrica Electrónica FPGA MATLAB Verilog / VHDL
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    Altera Quartus II Computer Aided Design Software and Modelsim-Altera Simulation Software Finalizado left

    Hi I need an expert in these two software Altera Quartus II Computer Aided Design Software and Modelsim-Altera Simulation Software. inbox me for more details.

    Altera Quartus Ingeniería eléctrica Ingeniería
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    Keypad 4X4 VHDL decoder Using VHDL: ModelSim altera/ Quartus/ Questasim Finalizado left

    1. Encode key presses on a standard 16-key 2. give a stable 4-bit binary output 3. Have output to indicate when a key is being pressed.

    Diseño de circuitos Electrónica FPGA Microcontrolador Verilog / VHDL
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    Create me a VHDL ping pong game using FPGA that has 1 player against computer, 2 players and 2 players against computer Finalizado left

    VHDL, DE2 Board 115, Ping pong game, max score is 16 and the ball speed should increase when the score is 10 and the ball color as well

    FPGA Verilog / VHDL
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    Create me a VHDL ping pong game using FPGA that has 1 player against computer, 2 players and 2 players against computer Finalizado left

    VHDL, DE2 Board 115, Ping pong game, max score is 16 and the ball speed should increase when the score is 10 and the ball color as well

    Ingeniería eléctrica Electrónica FPGA Microcontrolador Verilog / VHDL
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    Quran reader Finalizado left

    i need an mobile App . like house of Quran but i need it on mobile . with extra requirements.

    Android iPad iPhone Desarrollo de apps móviles
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    DDR3 layout in Altium Finalizado left

    Dissolve DDR3, FlyBy topology, 2 Altera SoC chips. 8 layers (S-P-P-S-S-P-P-S), 3 (4, 5, 8 layers) available for DDR wiring. Changing the placement of components is acceptable if critical. Alignment rules and signal classes are defined. Deadline until 28.02. It is possible to expand the order to a complete layout of the board with an increase in cost and extension of terms.

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    Разводка DDR3 в Альтиуме Finalizado left

    Развести DDR3, топология FlyBy, 2 чипа Altera SoC. 8 слоев (S-P-P-S-S-P-P-S), для разводки DDR доступно 3 (4, 5, 8 слои). Допустимо изменение размещения компонентов, если критично. Правила по выравниванию и классы сигналов заданы. Срок до 28.02. Возможно расширение заказа до полной разводки платы с увеличением стоимости и расширением сроков.

    Diseño de circuitos Ingeniería eléctrica Electrónica Diseño PCB
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    Tampermonkey - Script jogo Browser Finalizado left

    Preciso traduzir o script é altera algumas ações de acordo com minha necessidade tbm quero mudar sua interface para diminuir a poluição visual! Aceito dicas!! Então preciso das seguintes alterações: Traduzir todo código é nomes para português Mudar a interface "Painel" para diminuir a poluição visual é facilitar o uso! Corrigir algumas funções existente é tira os erros é má funcionamento. Tudo que precisa ser feito esta descrito abaixo: Adicionar as seguintes funções; 1) Compras Joias no leilão quando atingir certa quantidade na mão! 2) Compra merc Leilão quando tiver (X) valor em atributo (X) 3) Ven...

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    Need application level mathematics tutor Finalizado left

    Hi Looking for IIT standard application level maths tutor who is familiar with CBSE norms, short cuts and make maths much interesting for kids. It can be one to one individual attention for kid . Currently looking for someone who can make maths interesting, fun, knows indian curriculum...familiar with CBSE norms, short cuts and make maths much interesting for kids. It can be one to one individual attention for kid . Currently looking for someone who can make maths interesting, fun, knows indian curriculum. Extra knowledge about Abacus or Vedic maths is a plus. Portions can be start from base to approach level. It is for homeschoolers who can go way higher. If you are familiar with Nios curriculum also is a plus point. Need ur price monthly which an Indian middle class parent ca...

    Algoritmos Educación y tutoría Electrónica Matemáticas Mathlab y Mathematica
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    Frame Buffer Finalizado left

    Develop VHDL IPs for high speed read and write to DDR for image processing applications for NIOS based SoC designs

    Diseño digital FPGA Verilog / VHDL
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    Embedded Programming Finalizado left

    We are looking for a developer who has experiance in Embedded Application Programming. Typical Operating Systems Embedded Linux Android FreeRTOS μC/OS ARM, MIPS, Motorola, ST, TI, Microchip... Arduino Xilinx MicroBlaze (Softcore Processor) Xilinx and Altera FPGA (see Electronics Overview) Identifying and removing bottlenecks with performance analysis and tracing tools. Using low-level languages such as C or assembler for greater control over resource usage. Developing unit tests to quickly verify software modules on higher performance machines. Tuning code for low memory usage and looking for memory leaks using tools such as Valgrind. Preventing memory leakage by using static allocation if necessary (for example in a safety critical application). can develop user interfaces...

    Programación en C DDR3 (PCIe, board design/fpga) Software integrado FPGA FPGA Coding
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    Electrical Engineering/Altera Quartus/Logic Design Finalizado left

    I need guidance with Altera Quartus and introductory Logic Design/Electrical Engineering work.

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    Embedded System Finalizado left

    I am looking for an expert in DE2-115 board

    Programación en C Diseño digital FPGA Verilog / VHDL
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    Создание VHDL FPGA проекта для платы Altera DE2. Finalizado left

    Цветомузыка. Адресная светодиодная лента, фильтр по частотам (высокие, средние, низкие), в зависимости от громкости и частоты мигает лента разными цветами

    Ingeniería eléctrica Electrónica FPGA Microcontrolador Verilog / VHDL
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    8 bit Calculator VHDL with 4x4 Keyboard Finalizado left

    I need a project made with the software Quartus. My board is using an Altera chip, model: EP4CE6E22C8N. I need a 8 bit calculator, that uses a matrix 4x4 keyboard and display the results in the 7 seegments display that my board has. Board model: RZ-easyfpga a2.2 I attached on the job the pin diagram of my board.

    Ingeniería eléctrica Electrónica Ingeniería FPGA Verilog / VHDL
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    digital system design Assignment Finalizado left

    Its a digital system design homework using Altera’s Quartus II V13.0-SP1, and develop a Random Number Generator which will display random decimal numbers on the 7 segment displays of the DE2 board... It may includes ASM charts, verilog code, and simulation NOTE: need only assignment 1 mentioned in the attached word file.

    Altera Quartus ASM Arquitectura de software Verilog / VHDL
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    Altera Schematic Design Finalizado left

    Expert using Altera Schematic Design

    FPGA Verilog / VHDL
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    gateway de pagamento mercadopago - Iphp postgresql Finalizado left

    Gateway de pagamento mercadopago - Integrar meu sistema de pagamento com mercadopago Fluxo: 1 - Preciso listar 3 opções de assinatura - Mensal -Semestral -Anual 2 - Usuário clica redirecionado para o mercadopago. 3 - Mercadopago dá o retorno e altera o status numa tabela (Data do pagamento, forma de pagamento, ) Já existe um sistema com essas tabelas... não preciso que faça front para elas: ___________________ Tabela: tbl_pessoa ___________________ -cod_pessoa -ds_nome ___________________ Tabela: Assinatura ___________________ -cod_produto_assinado -ds_produto_assinado -periodicidade -nu_valor ---------------------------------------------------------- Tabela: Pagamentos_de_assinatura ---------------------------------------------...

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    Altera Triple Speed Ethernet implementation V2 Finalizado left

    My name is Idan and I'm electronic engineer student. In my application I need to implement a standard VHDL TCP/IP communication. In order to do that we need to interface the Altera Triple Speed Ethernet IP core. The the code, that will interface the Altera TSE IP core, will be commplitly managed by the VHDL side, with fully handshake for max speed. The minimum performent of the system will be throughput of 300Mps @ 1000Mbps linke @ full duplex mode. I've recently bought the DE2-115 EVM and I want to implement the on board Ethernet (with On-Board PHY Chip). The code will be evaluated with Wireshark (Optional: loop back between the two ports. I'm bacically want to have a quick ademenstration on any board that you'll have before adjust it to my pro...

    Ingeniería eléctrica Electrónica FPGA Microcontrolador Verilog / VHDL
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    FPGA/Altera Finalizado left

    I am looking for an expert in following: Cross-compile MT7688 CPU kernel MT7688 32/128MB CPU Quartus project,

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    Altera Cyclone IV FPGA connected using PCIx to Mediatek MT7688 32/128MB CPU in OpenWrt Finalizado left

    1. Cross-compile MT7688 CPU kernel, with enabled and working PCI express, write simple step-by step documentation, MT7688 must detect PCIx card connected, draw simple schematic with all necessary elements. 2. Make sample Quartus project, and write test app : 2.a. Use Hard IP pci x core on Cyclone IV, for example EP4CGX15 or similar 2.b Map PCI device memory space to read/wite access from MT7688 using DMA. Payload can be fixed size >=128 bytes per single R/W transaction. 2.c Write simple C program for OpenWrt to access PCI express device mapped memory read/write data using DMA. Project can be split to 2 parts. 1. and 2. If you can do only one part, contact us.

    Programación en C Programación en C++ Ingeniería eléctrica Electrónica Microcontrolador
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    Project for Swapnil P. Finalizado left

    can you make nios fake marksheet

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    Project for Swapnil P. - 17/09/2020 15:36 EDT Finalizado left

    can you make nios fake marksheet

    Diseño gráfico Illustrator Edición de fotos Photoshop Diseño con Photoshop
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    Simulated FPGA trojan Finalizado left

    As part of a technology demonstration project, we need a simulated malicious trojan embedded in some open source application (such as PipeCNN) running on an FPGA, preferably on a Terasic DE5-Net Altera Stratix V GX FPGA board. The simulated trojan should, upon trigger, use the PCIe bus to write a random value to some system RAM location (without causing the system to crash in process).

    Electrónica FPGA Coding PCI Express Verilog / VHDL
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    Altera Triple Speed Ethernet implementation Finalizado left

    My name is Idan and I'm electronic engineer student. In my application I need to implement a standard VHDL Triple Speed Ethernet Altera IP. I've recently bought the DE2-115 EVM and I want to implement the on board Ethernet (with On-Board PHY Chip).

    Altera Quartus FPGA Verilog / VHDL
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    FPGA Nios 2 developer Finalizado left

    I need test program for DE10-Lite board for UART communication. if you have experience, you can work remotely on my pc what was connected with the board. Quartus 18 was installed already with USB-UART converter. Bid on this project if you can do this. #1. Nios 2 UART test #2. communication with MCU (MCU part firmware prepared)

    Programación en C Ingeniería eléctrica Electrónica FPGA Verilog / VHDL
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    Nios2 developer for DE10-Lite board test Finalizado left

    hi, Hope to get help from someone who can program UART intercommunication with Nios II. if you have experience on NIOS II, feel free to ask me anytime. Thanks

    Programación en C Ingeniería eléctrica Electrónica Microcontrolador Verilog / VHDL
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    FPGA developer for Nios II Finalizado left

    hi Need to a test program Nios II for UART communication. It should be run on DE10-Lite kit with Quartus 18.1 Hope to keep the relation with experienced developer. With the experienced developer, I will move forward one by one, Thanks

    Ingeniería eléctrica Electrónica FPGA Microcontrolador Verilog / VHDL
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    Project for Duc D. Finalizado left

    Hi Duc D., tôi cần giúp làm FPGA Altera. Nếu giúp được, xin LL với tôi. Za lo, vi bơ của tôi là bay sau khong chin bay nam chin ba bay tam. Locson

    Ingeniería eléctrica Electrónica FPGA Escritura técnica Verilog / VHDL
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    Project for Khanh L. Finalizado left

    Hi Khanh L., tôi cần giúp làm FPGA Altera. Nếu giúp được, xin LL với tôi. Za lo, vi bơ của tôi là bay sau khong chin bay nam chin ba bay tam. Locson

    Bitcoin Cadena de bloques Programación en C Programación en C++ Electrónica
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    Project for Kevin N. Finalizado left

    Hi Kevin N., tôi cần giúp làm FPGA Altera. Nếu giúp được, xin LL với tôi. Za lo, vi bơ của tôi là bay sau khong chin bay nam chin ba bay tam. Locson

    Adobe Lightroom Software integrado Fotografía Programación de proyectos Verilog / VHDL
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