Verilog vhdltrabajos

Hi, I am looking for a good Verilog coder who can code some basic logic design. PM me if you would like to know more. I would like it done by Thursday so if you take the project, you will be given two days at most to complete it. I prefer it to be done in a day. It shouldnt take more than an hour or two if you're familiar with Verilog. Thank you

This project is on VHDL need to be professional in VHDL the information is given in the attached in the document. 1. Modify and utilise the provided behavioural model for a 4-bit register, to compile, simulate and verify correct functional operation of an 8-bit device.( behavioral model for a 4-bit register provided at the end of the page) 2. Modify the dataflow architecture (figure 1) to facilitate the implementation of the complete instruction set (table 1). Note: special attention will need to be given to the inclusion of a shifter and execution of the increment and decrement instructions. 3. Design and individually simulate behavioural VHDL models for the dataflow components. Combine structurally to define the complete dataflow

I am in need of a fully working design of an FPGA based oscilloscope, Must be at least 20 Mhz and bidder must provide full analog front end circuit and VHDL code to view the output on a PC via USB or Ethernet. Work must be your own.

We need a pipelined verilog datapath that is formatted to MIPS ISA. We can provide you a non pipelined datapath to use as a reference. We have also included a non-pipelined and pipelined image of what the datapath should look like. It will need to be able to input MIPS assembly code into the program via a .txt file. Additionally, we need this datapath and assembly code to be able to be synthesized on a Spartan 3E FPGA board. Overview: -Design a pipelined version of the datapath - Synthesize the design - Run it on FPGA board using our assembly code - Use the LCD of the FPGA board to display the coordinates of the block with the minimum SAD.

To utilise structural and behavioural VHDL to model and simulate an 8-bit processor capable of implementing the attached instruction set. VHDL have to be used. For designing need multisim.

Hi, I need a state machine that controls the Wiznet chip W5300 for UDP or Ethernet communication. The scope is to send data on ethernet at (at least) 10 Mbit/s. The state machine should be in Verilog (not VHDL) targeting an FPGA. Further datails in PM.

Por favor, regístrate o inicia sesión para ver los detalles.

Por favor, regístrate o inicia sesión para ver los detalles.

I need you to do the following parts in the previous VHDL report that you have done for me . Before I hire you please agree to me that you will do all the required and amend them the report where also you will need to amend the result and discussion parts . 1)Do error codes control based in the Linear Sequential System and amend it on the report and in the code in the 7/4 decoder and in the 15/11 decoder and the generic code. Please you must to use error codes check in the 7/4 decoder, 15/11 decoder and in the generic code . please amend it in the report and in the codes . 2) Do full LSS simulating the 7/4 decoder using TIMING analysis .It is in section 3b .You have to do it in the code and in the report. 3) You nee to You write about Timing and what is the difference betwe...

Using VHDL language, QUARTUS II software and ALTERA DE2 board, you should design, simulate, and implement an 8-bit ALU circuit. This circuit will take two 8-bit unsigned binary numbers, operate on them, and display the result. ? First, the 7-segment display should display "S0" to indicate "State 0". When a push button on the DE2 board (e.g. KEY1) is pressed, the 8-bit value provided on the Toggle Switches SW7 to SW0 (operand1) should be stored in a register. Note that SW7 is the MSB and SW0 is the LSB. ? The 7-segment display should then display "S1" to indicate "State 1". When the push button is pressed again, the 8-bit value provided on the Toggle Switches SW7 to SW0 (operand2) should be stored in a register. ? The 7-segment display sh...

I need a verilog coder to code a simple ALU type operation. test bench, guide, inputs, specifications, will be given. You just have to code verilog file. I wil tell you details in message, but code I require is simple. So budget is not very high. I give preference to people with lower bid and good history/ratings. THIS is NOT VHDL CODING. Only, people with experience in verilog should apply. PLease tell me your experience is verilog and I wil provide you more details about project. If you can send me any of verilog file you have coded ; I will look and your skill/knowledge and will give preference to people who can provide example of their code. Deadline is 7-10 days.

Hi, I need a person who can do a verilog job for me. More details will be provided in PM. If you previous work sample on Verilog then it would be plus. Would be waiting for your bids. Thanks

Por favor, regístrate o inicia sesión para ver los detalles.

Hi, I need a person who can do a simple verilog job for me. More details will be provided in PM. If you previous work sample on Verilog then it would be plus. Would be waiting for your bids. Thanks

Hi, I need a verilog HDL code for a simple project, the project is as follows: you start off as a single blue square on the bottom of the screen(background black), then once the game starts, blocks(red squares) start falling from the top of the screen and you use KEY[1]and Key[2] on the DE2 board as controls to move your square right/left to dodge the falling blocks. if you get hit by a falling block the game terminates and goes back to it's original state(a single blue square at bottom of screen). the below is the vga adapter we use module part1(SW,KEY,CLOCK_50,VGA_R, VGA_G, VGA_B, VGA_HS, VGA_VS, VGA_BLANK, VGA_SYNC, VGA_CLK,LEDR); input CLOCK_50; input [17:0] SW; input [3:0] KEY; output [17:0]LEDR; output [9:0] VGA_R; output [9:0] VGA_G; output [9:0] VGA_B; out...

Hi there, I am looking for a digital designer with experience in VHDL, preferrable on ASIC, but FPGA will be considered as well. I am working on a complex project that will last a long time and I need help with development. Experience with Ethernet, LVDS or DDR would be a plus. I will first start with a small task to ensure that everything goes fine. Once that ends I will provide more and more work. Thank you. Regards, Nick Keywords: VHDL, digital design, electronics, VLSI, ASIC, FPGA

Face Recognition using Eigenfaces in FPGA HDL : Verilog Softwares: Modelsim, ALTERA Quartus II FPGA: ALTERA Cyclone II Need to simulate and synthesize eigenfaces for face-recognition in a FPGA. Eigenfaces for recognition by Matthew Turk and Alex Pentland ( IEEE paper) is the core of this project. Eigenfaces method is the core of this project, which is explained in detail in Eigenfaces for recognition by Matthew Turk and Alex Pentland. This method has been implemented successfully in MATLAB and the code is also freely available, but it has not been implemented in FPGA's extensively due to the memory and processing speed constrains. The Pixel information from greyscale face images (up to 5 images can be used & face images should be from approved face data...

Face Recognition using Eigenfaces in FPGA HDL : Verilog Softwares: Modelsim, ALTERA Quartus II FPGA: ALTERA Cyclone II Need to simulate and synthesize eigenfaces for face-recognition in a FPGA. Eigenfaces for recognition by Matthew Turk and Alex Pentland ( IEEE paper) is the core of this project. Eigenfaces method is the core of this project, which is explained in detail in Eigenfaces for recognition by Matthew Turk and Alex Pentland. This method has been implemented successfully in MATLAB and the code is also freely available, but it has not been implemented in FPGA's extensively due to the memory and processing speed constrains. The Pixel information from greyscale face images (up to 5 images can be used & face images should be from approved face data...

To create a "checker" in a Network Interface. 1. Checker will collect 32 bits data from 8 deserialisers. (eg A1 ~A8) 2. Checker will collect 32 bits data from 3 Collectors. (eg C1~C3) 3. Checker will then compare the data if it matches. (eg C1 = A1~A8?, C2 = A1~A8?, C3 = A1~A8?) 4. If data matches, Checker will release the data, (eg if C1 = A5 release data , if C2 =...Checker will then compare the data if it matches. (eg C1 = A1~A8?, C2 = A1~A8?, C3 = A1~A8?) 4. If data matches, Checker will release the data, (eg if C1 = A5 release data , if C2 = A1 release data, if C3 = None delete C3) 5. continue process. I attached a picture and original source code for Network interface. "Checker " is to target on at the Receiver. Preferably using Xilinx in VHDL...

To create a "checker" in a Network Interface. 1. Checker will collect 32 bits data from 8 deserialisers. (eg A1 ~A8) 2. Checker will collect 32 bits data from 3 Collectors. (eg C1~C3) 3. Checker will then compare the data if it matches. (eg C1 = A1~A8?, C2 = A1~A8?, C3 = A1~A8?) 4. If data matches, Checker will release the data, (eg if C1 = A5 release data , if C2 = A1 release ...3. Checker will then compare the data if it matches. (eg C1 = A1~A8?, C2 = A1~A8?, C3 = A1~A8?) 4. If data matches, Checker will release the data, (eg if C1 = A5 release data , if C2 = A1 release data, if C3 = None delete C3) 5. continue process. I attached a picture and original source code for Network interface. "Checker " is to target on at the Receiver. Preferably using Xilinx in VHDL...

I am running a big project and am currently time constrained to implement the Ethernet connection. This is a fairly easy project for someone with expertise in Verilog. The deliverables are as follows -Verilog code to run on a Spartan 6 Atlys Board - (xc6slx45) -simulation time diagrams (more details will be given to the winner) - The code should be able to transmit and receive data at 100mbs (1Gbps support would be nice but not a must) -Support a multicasting protocol (In that if I wanted to send data to 3 recepients out of 5 in the network, I should be able to do it easily) -Support for broadcasting (be able to make the system send the data to all recepients in the network when needed) -there are existing IPcores that offer a starting point and I would suggest tha...

1) Design and build a 8-bit adder using structural or behavioral verilog code. Account for an initial carry-in bit. 2) How to start ? 3) Verilog code in either structural or behavioral format Test bench and simulated waveforms showing the inputs and outputs. Add the 8-bit numbers: 50 + 120 with initial carry in of 0 80 + 75 with initial carry in of 1 225 + 142 with initial carry in of 0 180 + 75 with initial carry in of 1

I'm working on the VHDL programming for my thesis and one of my task is to write the code for a simple Hello program. The message on the LCD screen should be able to blink on toggling one of the switches. I'm not sure how to make a start on this. Also, there are few things I would like to ask before starting working on it. For further information please contact me on this website. Thanks

Create a project in Xilinx ISE that uses the OpenCores tri-mode MAC that works on the Xilinx SP605 Spartan 6 LX45 evaluation board. You can use one of the existing Xilinx demo projects as a base, or anything t...can be a peripheral that just replaces the existing Xilinx peripheral in an EDK design, or it could just be a stand-alone project. Basically, for anyone that already has already used the OpenCores tri-mode MAC at a gigabit on the SP605, this project is probably just a matter of exporting one of your test projects. The project MUST be in VHDL, sorry Verilog not accepted under any circumstances (except for any OpenCores code that is wrapped with VHDL). No payment up front, but 25% payment considered before delivery if you provide a VNC view of the code ...

Need to evaluate the FPGA prototyping board Altera cyclone 2 DE1 to design a voice recorder. Design the project using design should be able to record a minimum of 1 minute of audio input and playback clearly through the on-board speaker or an external speaker. In need of the VHDL programme codes and a Report on the analysis and how the design is done.

Xilinx ISE Project – VHDL design for Virtex 6 FPGA The task is to create a Xilinx ISE project to work with the Xilinx ML605 development board and a mating DAC board. The DAC board comes from a company called 4DSP, model FMC204. See Handbook for FMC204 board attached. The ML605 from Xilinx is a development board for the Virtex 6 FPGA. See The FMC204 board plugs into the ML605 via the high density FMC connector. The project is to generate a simple sine wave at 28MHz in the FPGA and have the DAC board produce 4 analogue output signals. The clock on the DAC board is to run at 112Mhz and provide a reference clock to the FPGA. The DAC sample frequency is also 112Msps. There are

1. SAR ( synthetic aperture imaging radar )- 2. detection algorithm 3. compression algorithm all these 3 developed in VHDL or may in matlab FFT - in FPGA ( field programming gate array ) parallel and make a architecture with VHDL and compare with different software

1. SAR ( synthetic aperture imaging radar )- 2. detection algorithm 3. compression algorithm all these 3 developed in VHDL or may in matlab FFT - in FPGA ( field programming gate array ) parallel and make a architecture with VHDL and compare with different software

I want to protect my IP cores, targeting Xilinx FPGAs, by using a 1-Wire EEPROM with SHA engine. It is explained in Xilinx application note xapp780 how it can be made. The vhdl source codes as well as picoblaze processor source codes for the xapp780 can also be downloaded from the Xilinx website. The problem is that the xapp780 is for DS2432 EEPROM from Maxim IC. However, I want to use DS28E01-100 EEPROM instead. I compiled the sources but the design is not working with DS28E01-100 EEPROMs. Some more points: 1 - You have to change the xapp780 sources so that it it works with DS28E01-100 EEPROM. 2 - We need 2 designs as it is in xapp780, loader and tester. Loader programs the EEPROM with our security key. Tester checks if the SHA keys are matching. 3 - Target FPGA is X...

You need to model a "Combination lock" state machine that activates an "unlock" output when a certain binary sequence received: Please see the attached file ## Deliverables see attached

We are looking for someone who has worked with the Xilinx Endpoint Block for PCI Express before and sets up an example project for us. ## Deliverables It does not matter what variant of the endpoint block you have used before, but you must have developed code to control it your self, not just instanciated some third party wrapper like EZDMA. Our development will be done in VHDL. If you have a software setup that allows you to simulate the endpoint block together with the GTP we can outsource also the validation to you.

I need VHDL code written for a Nexys2 Board from Digilent, Inc. that focus only on the refresh rate of the VGA Monitor displaying in the color black and White. Each color should be connected to a switch so I can test good and bad refresh rates for each separate color on the monitor. I will need the syntax written for the UCF file to correctly connect to the Nexys2 board to perform testing of the code. I will need instructions on how to manually change the refresh rates in the code myself so I can use Xilinx ISE Design Suite 13.1 to generate a bit file that will be loaded to the board with Adept Software. I need to be able to set good and very bad refresh rates to record for my research for each color.

Por favor, regístrate o inicia sesión para ver los detalles.

Hello I want a vhdl code for a digital clock to present hours and minutes in board of spartan 3 . The code should be wrriten by the freelancer him/her self not from copy from internet. A report should be included . Thank you

Processor Implementation in VHDL codes are in pdf. compile it and correct the errors. it has to work at XILINX 10.1 just create an errorless project. all codes are ready in pdf. MAX 60$. WORKING SIMULATION IS ENOUGH. CORRECT ERRORS, maybe there is no error but i can not run simulation. URGENT.

I'm working on a small project which implements a simple (slow) serial CPU bus in a FPGA. The CPU bus is 2 bits wide and uses a transition based protocol. The code is written in VHDL and functional but the system contains bugs. You will review my code, consult me how to improve it and try to find bugs. The code base is only a few hundred lines and is simple in nature. The bug(s) can be in the code but also in my physical setup. Communication will go through a chat application such as MSN, Google Talk, IRC (I'm open to alternatives). My timezone is GMT+2. I expect you to have a good knowledge of VHDL, Experience with Altera FPGA and the Quartus II development environment, basic to good knowledge of digital electronics. A bonus upon succesful completi...

This project implements almost all the mips instructions, more instructions can also be added. it can also be used in multicycle or pipelined processor

Opracowanie oraz zapisanie w języku opisu sprzętu (HDL) zadanej funkcji systemu wbudowanego typu NoC. Realizacja – dowolne ze środowisk do opisu/syntezy/symulacji systemów cyfrowych. A temat to: Moduł mechaniki przełączania w ruterze typu store-and-forward. Przyjąć, że ruter jest 5-portowy (N, S,W, E, LP) z n-flitowym buforem wejściowym (n przyjąć z zakresu 5-20). Opracować przykładowy format flita. Można przyjąć, że pierwszy flit zawiera ID portu, do którego ma być przekierowana transmisja (rozmiar bufora FIFO ma pomieścić całą transmisję).

I have an Altera DE2-115 evaluation board with a Cyclone 4 FPGA processor (EP4CE115F29C7). I need a HDL design either written in Verilog or VHDL that implements a SPI core. I want to transfer data between the FPGA evaluation board and a PIC24 microprocessor evaluation board from Microchip. The data consists only of a few bytes that are transferred in both directions approximately every second. The HDL design must be written so that i can use it directly in Quartus II software by embedding the SPI core into a top level schematic file. You should only make a bid if you are familiar with Quartus II and if you have the necessary hardware to test your SPI HDL design, or if you have so much experience with FPGA SPI that you are very confident that your design will work.

Finalise the VHDL code and test bench. Prepare the final report. This MUST be consolidated into a single report for the overall task, but will clearly show the contributions of the various sub-tasks. The report should include at least the following items: i. a complete functional description of the system. Also include a block diagram of your synthesized design ii. a description of how the system has been mapped onto the board resources, including pin-outs and include a summary of the FPGA resources used. iii. A discussion of the simulation rationale (i.e. what you were trying to achieve) and the results – annotated in a manner that makes is completely clear that you have achieved what you se...

Roughly what you have to do is: Write an emulator for the ARM machine. This should have a range of features to show the inner workings of the process of executing an assembly program. Write a bubble sort program in ARM assembly. The start of this file is provided, you have to fill in the blanks. Stage 1 Write an emulator that is able to read a ".emu" file in the format described above and detect programs that are not correct such as having more or less than 32 bits per line, or that have non recognized instructions such as unknown opcodes. The program should be written so it is executed using a command similar to ./emu [option(s)] Stage 2 Implement the option "-trace" which should show how the program is executed and how the different registers are affe...

it's about writing a very basic, single-cycle cpu that just operates : add,load,store,beq and slt in VHDL. im gonna pay 45$ for that and i have almost 3 days left. for some one who knows VHDL or assembly language doest take more than a day.I have attached the project question and i can provide you the link for VHDL download if interested in doing that. I have already done the data path design and the control unit, So all i need is just the VHDL codes.

(1). Write VHDL code for entity **1-of-2 multiplexer**, synthesis and implement the design. Present your synthesis result, check summary report and identify the recourses used. Write another architecture description then compare the implementation results. (2). Write VHDL code for entity **BCD-7-segment converter**, synthesis and implement the design. Present your synthesis result, check summary report and identify the recourses used. Write another architecture description then compare the implementation results. (3). Write VHDL code for entity **decoder**, synthesis and implement the design. Present your synthesis result, check summary report and identify the recourses used. Write another architecture description then compare the implementation results. (4). Wr...

...NiosII based music player that allows the user to select the music via a touch screen. the player must satisfy thses requirements: 1. the touched images must be 64*64 pixel by 64 pixel each.( the type of lcd should be LTM)(vhdl code) 2. the player must have at least three music selections each in at last ten second long. for the 3 songs, need to program the flash memory with the wav file which consist of 3 songs should be 48 khz for each pice of music(C code) 3. Need to creat PLL (phase-lock-loop) to generate the 18.432 MHZ clock signal for the codec:(the vhdl code need for a component in the niosII system that contain a 128*32 first-In-First Out memory and wolfson WM8731 codec data interface. fifo(altera dcfifo) 4. the top design need Wolfson WM8731 Codec Control i...

hi! i am looking for the VHDL code for DCT implementation. pls help me out.

Here is a description of the project I'm needing, the first part (written plan of implementation) is due Tuesday morning. The final project is due May 10. It needs to be created using VERY basic Verilog code for use on an Altera DE2 board. Please email with questions. "You are the design engineer and must create a working Mastermind game using the Altera DE2 board. You may use Verilog modules and any of the logic gates and library parameterized modules. You may not use any other programming language such as C. Your game must at a minimum allow one human to play one game, either against another human or the computer. It is up to you to decide how to 1) represent the colors 2) the codemaker will enter and store the code. 3) The codebreaker will enter a guess...

Por favor, regístrate o inicia sesión para ver los detalles.

Serial Peripheral Interface is basically used to allow the Microcontroller unit to communicate with many peripheral devices. The serial clock synchronises the shifting data serially through two serial lines. Master controls the interchange by controlling the clock line. SPI is a synchronous serial data bus. This report describes the design of Serial Peripheral Interface using VHDL and simulate using simulator. The transmitting and receiving parts are designed by taking the logic from the Parallel–in Serial–out shift register and Serial –in Parallel–out shift register. SPI interface is designed and then it is interfaced with Microcontroller bus interface. The microcontroller bus interface is designed to read, write and data transfer with the registers .Basica...

Please help me to implement the MPIS single cycle CPU

Skills required: * Experience with Xilinx Virtex-5 or Virtex-6 FPGA * Experience with Xilinx EDK designs * Competent in VHDL Extras: * Experience with XUPV5 development board * Access to a XUPV5 development board The job is to develop a peripheral core in VHDL and a test project for EDK to verify the core on the XUPV5 board. The peripheral will use the PCI Express Endpoint internal core of the Virtex-5 FPGA and provide a user FIFO interface. The peripheral will contain a DMA scatter gather engine to enable the software in the host PC to setup DMA transfers between the host PC and the FIFOs. There will be 8 FIFOs (or channels) that can be targeted by the host software.